`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/04/10 19:12:03
// Design Name: 
// Module Name: fifo_read
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module fifo_read(
    input wire sys_clk, //系统时钟50MHz
    input wire sys_rst_n, //全局复位
    output reg pi_flag, //并行数据有效标志信号
    input wire tx_ready, //串口发送数据准备好标志信号
    output reg fifo_read_en, //FIFO读使能信号
    input  fifo_empty//FIFO读空标志信号
    );
    // State machine states
    localparam IDLE = 2'd0, READ = 2'd1,SEND = 2'd2;
    reg [1:0]state;

    always @(posedge sys_clk or negedge sys_rst_n) begin
        if (!sys_rst_n) begin
            state <= IDLE;
            fifo_read_en <= 1'b0;
            pi_flag <= 1'b0;
        end else begin
            case (state)
                IDLE: begin
                    pi_flag <= 1'b0;
                    if (tx_ready&(~fifo_empty)) begin
                        fifo_read_en <= 1'b1;
                        state <= READ;
                    end else begin
                        fifo_read_en <= 1'b0;
                    end
                end
                READ: begin
                    fifo_read_en <= 1'b0;
                    pi_flag <= 1'b1;
                    state <= SEND;
                end
                SEND: begin
                    fifo_read_en <= 1'b0;
                    pi_flag <= 1'b0;
                    state <= IDLE;
                end

                default: state <= IDLE;
            endcase
        end
    end

endmodule
